Cypress NoBL CY7C1371D user manual

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1. Cypress NoBL CY7C1371D user manual

CY7C1371D CY7C1373D CYPRESS PERFORM Features 18 Mbit 512K x 36 1M x 18 Flow Through SRAM with NoBL Architecture Functional Description 111 No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles Supports up to 133 MHz bus operations with zero wait states Data is transferred on every clock Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to el
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