17th Telecommunications forum TELFOR 2009 Serbia Belgrade November 24 26 2009 VIRTEX II Timing Simulation vs Reality Silvana POPESCU Aurel GONTEAN Abstract The goal of this paper is understanding the performance capability of a modern FPGA in a post layout simulator using a typical design For this an eight phase generator was used as a test circuit and the delays between the outputs have been evaluated and corrected Keywords FPGA rise time simulation VH
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