440GX Application Note Migrating to PPC440GX from PPC440GP Software Considerations AMEG January 22 2008 APPLIED MICRO CIRCUITS CORPORATION Introduction This document describes the changes between the AMCC PowerPC 440GP and 440GX from a software perspec tive The 440GX User s Manual and related documents will discuss the changes in detail The purpose of this document is to highlight the changes and identify the areas where software updates may be necessary The reader
440GX Application Note DDR Read Data Path Tuning and the Internal Digital Delay Line AMCG January 18 2008 APPLIED MICRO CIRCUITS CORPORATION Abstract The DDR SDRAM controller used in the AMCC PowerPC 440GP and the PowerPC 440GX supports a wide variety of memory architectures including point to point SO DIMMs and DIMMs In order to support these memory sys tems the DDR memory systems read and write timings must be adjustable over a limited range of time values These
L440GX Server Board Product Guide Order Number 722077 005 Disclaimer Intel Corporation Intel makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Intel assumes no responsibility for any errors that may appear in this document Intel makes no commitment to update nor to keep current the information contained in this document No part of this document may be c
Intel 440GX AGPset Design Guide March 1999 Order Number 290651 001 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel pro
Preliminary Features 440 processor core operating up to 800 MHz with 32 KB l and D caches with parity checking On chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory Selectable processor bus clock ratios Refer to the Clocking chapter in the PPC440GX Embedded Processor User s Manual for details Double Data Rate DDR Synchronous DRAM SDRAM interface operating up to 166 MHz External Peripheral Bus 32 bits
AMEE APPLIED MICRO CIRCUITS CORPORATION Part Number 440GX Revision 1 20 June 9 2009 440GX Data Sheet Power PC 440GX Embedded Processor Features PowerPC 440 processor core operating up to 667 MHz with 32KB and D caches with parity checking On chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory Clocking chapter in the PPC440GX Embedded Processor User s Manual for details Double Data Rate DDR Synchronous DR
Intel 440GX AGPset Design Guide March 1999 Order Number 290651 001 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel pro