Freescale Semiconductor DSP56301PB Product Brief Rev 2 11 2005 DSP56301 24 Bit Digital Signal Processor The DSP56301 is a member of the DSP56300 core family of programmable CMOS DSPs This family uses a high performance single clock cycle per instruction engine Significant architectural features of the DSP56300 core family include a barrel shifter 24 bit addressing instruction cache and DMA The DSP56301 performs at 66 80 100 MIPS using an internal 66 80 100 MHz clock a
MM MOTOROLA Chip Errata DSP56301 Digital Signal Processor Mask 1F92R General remark In order to prevent the use of instructions or sequences of instructions that do not operate correctly we encourage you to use the lint563 program to identify such cases and use alternative sequences of instructions This program is available as part of the Motorola DSP Tools CLAS package Silicon Errata Errata Applies No Errata Description to Mask Description added 5 1 1996
Freescale Semiconductor DSP56301 Technical Data DSP56301 24 Bit Digital Signal Processor MEDI The DSP56301 is intended Program X Data Y Data for general purpose digital RAM 2 signal processin 4096 x 24 bits 2048 x 24 2048 24 signat 55118 Default bits bits particularly in multimedia Default Default and telecommunication Peripheral applications such as video Expansion Area conferencing and cellular External Gener